The minimum feature sizes of integrated circuits (ICs) have been shrinking for years. Commensurate with this size reduction, various process limitations have made IC fabrication more difficult. One area of fabrication technology in which such limitations have appeared is photolithography.
Photolithography involves selectively exposing regions of a resist coated silicon wafer to a radiation pattern, and then developing the exposed resist in order to selectively protect regions of wafer layers.
An integral component of photolithographic apparatus is a “reticle” which includes a pattern corresponding to features at one layer in an IC design. The reticle typically includes a transparent glass plate covered with a patterned light blocking material such as chromium. The reticle is placed between a radiation source producing radiation of a pre-selected wavelength and a focusing lens which may form part of a “stepper” apparatus. Placed beneath the stepper is a resist covered silicon wafer. When the radiation from the radiation source is directed onto the reticle, light passes through the glass (regions not having chromium patterns) projects onto the resist covered silicon wafer to produce photo-generated acid. The resist is typically baked to undergo chemical changes that alter its dissolution properties. Subsequent development process is needed to obtain the relief image on wafer. In this manner, an image of the reticle is transferred to the resist.
As light passes through the reticle, it is refracted and scattered by the chromium edges. This causes the projected image to exhibit some rounding and other optical distortion. Furthermore, resist processing effects during the bake process, such as nonlinear diffusion of the photo-generated acid, exacerbate the pattern distortion on the wafer. Subsequent pattern transfer processing effects, such as etch bias, further degrade the pattern fidelity. While such effects pose relatively little difficulty in layouts with large feature sizes (e.g., layouts with critical dimensions above about 1 micron), they cannot be ignored in layouts having features smaller than about 1 micron. The problems become especially pronounced in IC designs having feature sizes near the wavelength of light used in the photolithographic process.
To remedy this problem, a reticle correction technique known as optical and process corrections (OPC) has been developed. Optical and process corrections involve adding dark regions to and/or subtracting dark regions from a reticle design at locations chosen to overcome the distorting effects of diffraction and scattering. Typically, OPC is performed on a digital representation of a desired IC pattern. First, the digital pattern is evaluated with software to identify regions where optical distortion will result. Then the optical proximity correction is applied to compensate for the distortion. The resulting pattern is ultimately transferred to the reticle glass.
In addition, a technique related to OPC, which improves the depth of focus, involves the use of modified subresolution assist features (SRAFs). FIG. 1 is an top plan view of a test pattern on a mask utilizing SRAFs. Typically, SRAFs 10 are located near open-ended edges 12a of features 12, although they can be utilized wherever corrections are necessary. SRAFs 10 reduce proximity effects without projecting an image onto the resist.
The degree of correction or the location of a SRAF for a given feature is determined largely by empirical methods. That is, experiments are conducted with reticles having “test” patterns to determine the illumination pattern produced on a wafer by light shown through the test pattern. The deviation between the actual illumination pattern and the desired feature pattern is used to determine how much correction is required for a reticle used to produce the desired feature pattern.
Each correction applies only to the pattern having the exact size and geometry as that tested. If the width of a feature or the separation between features changes, the correction also changes. Thus, given the huge range of IC feature variations, a potentially infinite number of test reticles would have to be produced to account for every pattern that might be encountered. To avoid this cumbersome task, exposure-latitude-based image intensity characteristics, such as image slope, maximum intensity, and minimum intensity, have been utilized to estimate the correction necessary for a particular feature.
While this approach provides some starting point, those skilled in the art will appreciate that lithography process performance is governed by depth-of-focus characteristics as well as exposure latitude. By utilizing only exposure latitude based image intensity characteristics, an undesirably large set of data values is required to ensure adequate modeling. Moreover, exposure latitude based image intensity characteristics provide no guidance as to where to locate SRAFs.
Accordingly, what is needed is an improved system and method for accurately estimating the degree of optical and process correction necessary for a given feature. The system and method should take into consideration exposure latitude and depth of focus characteristics. The present invention addresses such a need.